Masked Interrupt Status register
| RESERVED | Reserved. The value read from a reserved bit is not defined. |
| FUFMIS | FIFO underflow masked interrupt status. Set when the both the FUFRIS bit in the LCD_INTRAW register and the FUFIM bit in the LCD_INTMSK register are set. |
| LNBUMIS | LCD next address base update masked interrupt status. Set when the both the LNBURIS bit in the LCD_INTRAW register and the LNBUIM bit in the LCD_INTMSK register are set. |
| VCOMPMIS | Vertical compare masked interrupt status. Set when the both the VCompRIS bit in the LCD_INTRAW register and the VCompIM bit in the LCD_INTMSK register are set. |
| BERMIS | AHB master bus error masked interrupt status. Set when the both the BERRAW bit in the LCD_INTRAW register and the BERIM bit in the LCD_INTMSK register are set. |
| RESERVED | Reserved. Read value is undefined, only zero should be written. |